// **************************************************************
// COPYRIGHT(c)2016, Xidian University
// All rights reserved.
//
// IP LIB INDEX :  
// IP Name      :      
// File name    :  
// Module name  :  
// Full name    :  
// Time         : 2016 
// Author       : Wang-Weina 
// Email        : 327422289@qq.com
// Data         : 
// Version      : V 1.0 
// 
// Abstract     :
// Called by    :  
// 
// Modification history
// -----------------------------------------------------------------
// 
// 
//
// *****************************************************************

// *******************
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 

// *******************
// INFORMATION
// *******************

//*******************
//DEFINE(s)
//*******************
//`define UDLY 1    //Unit delay, for non-blocking assignments in sequential logic

//*******************
//DEFINE MODULE PORT
//*******************
//ram\u7684\u5730\u5740\u4e3a  19-15\uff1a\u89c4\u5219\u53f7\uff1b14\uff1a1\uff1b13-9\uff1aram\u53f7\uff1b8-0\uff1aram\u4e2d\u7684\u5730\u5740\u53f7
module rbve_256#(
    parameter RANGE_L=256,            
    parameter LOG2R  =5  ,
    parameter SUBR   =16 ,
    parameter RULE_SUM=32,
    parameter LOGBR  = 5 ,
    parameter PIPE_NUM=16 
    )
   (
    input wire clk,
    input wire rst_n,
    input wire [11:0]ram_dp_cfg_register,
    input wire lookup_en,
    // input wire[31:0] ram_ctrl,
    input wire cpu_wen,
    // input wire cpu_wen1,
    // input wire cpu_wen2,
    input wire[14:0] ram_addr,
    // input wire[15:0] ram_addr,
    input wire[95:0] ram_data,//
    input wire cpu_ren1,
    input wire cpu_ren2,
    input wire[RANGE_L-1:0] range,
    output wire[0:RULE_SUM-1] match,
    //output wire match_is,
    output wire lookup_done,
    output reg[31:0] read_data_cpu1,
    output reg[31:0] read_data_cpu2,
    output reg       read_data_valid1,
    output reg       read_data_valid2
    ); 

//*******************
//DEFINE LOCAL PARAMETER
//*******************
//parameter(s)
                                 
//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS
reg[0:RULE_SUM-1] valid;
reg[PIPE_NUM-1:0] mod_en;
reg[95:0] cpu_data_d1;
reg odd;
reg[95:0]read_data_cpuo1;
reg[95:0]read_data_cpuo2;
reg cpu_en_read1_d1,cpu_en_read1_d2,cpu_en_read1_d3,cpu_en_read1_d4;
reg cpu_en_read2_d1,cpu_en_read2_d2,cpu_en_read2_d3,cpu_en_read2_d4;
reg [14:0]ram_addr_d1,ram_addr_d2,ram_addr_d3,ram_addr_d4;
//WIRES

wire[95:0] cpu_data_o0,cpu_data_o1,cpu_data_o2,cpu_data_o3,cpu_data_o4,cpu_data_o5,cpu_data_o6,cpu_data_o7,cpu_data_o8,cpu_data_o9,cpu_data_o10,cpu_data_o11,cpu_data_o12,cpu_data_o13,cpu_data_o14,cpu_data_o15;
wire lookup_done0,lookup_done1,lookup_done2,lookup_done3,lookup_done4,lookup_done5,lookup_done6,lookup_done7,lookup_done8,lookup_done9,lookup_done10,lookup_done11,lookup_done12,lookup_done13,lookup_done14;
wire match_is_0,match_is_1,match_is_2,match_is_3,match_is_4,match_is_5,match_is_6,match_is_7,match_is_8,match_is_9,match_is_10,match_is_11,match_is_12,match_is_13,match_is_14;
// wire cpu_en_del;
wire cpu_en_mod;
wire cpu_en_read1;
wire cpu_en_read2;
reg[7:0] addr_loc;
// wire[LOG2R-1:0] rule_loc;
wire[LOGBR-1:0] ram_loc;
wire[RANGE_L-1-16 :0] range0;
wire[RANGE_L-1-32 :0] range1;
wire[RANGE_L-1-48 :0] range2;
wire[RANGE_L-1-64 :0] range3;
wire[RANGE_L-1-80 :0] range4;
wire[RANGE_L-1-96 :0] range5;
wire[RANGE_L-1-112:0] range6;
wire[RANGE_L-1-128:0] range7;
wire[RANGE_L-1-144:0] range8;
wire[RANGE_L-1-160:0] range9;
wire[RANGE_L-1-176:0] range10;
wire[RANGE_L-1-192:0] range11;
wire[RANGE_L-1-208:0] range12;
wire[RANGE_L-1-224:0] range13;
wire[RANGE_L-1-240:0] range14;
wire[0:RULE_SUM-1] match0,match1,match2,match3,match4,match5,match6,match7,match8,match9,match10,match11,match12,match13,match14,match15;
//*********************
//INSTANTCE MODULE
//*********************

 rbve_line #(.RANGE_L(256),
            .SUBR(16))
 U_line0(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .en_in(lookup_en),
    .lookup_en(lookup_en),
    .mod_en(mod_en[0]),
    .odd(odd),
    .addr_loc(addr_loc),
    .cpu_data(cpu_data_d1),
    .cpu_data_o(cpu_data_o0),
    .range(range),
    .range_out(range0),
    .match_in(32'hffffffff),
    .match_out(match0),
    .match_is(match_is_0),
    .lookup_done(lookup_done0)
    );
 rbve_line #(.RANGE_L(240),
            .SUBR(16))
 U_line1(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .en_in(match_is_0),
    .lookup_en(lookup_done0),
    .lookup_done(lookup_done1),
    .mod_en(mod_en[1]),
    .odd(odd),
    .addr_loc(addr_loc),
    .cpu_data(cpu_data_d1),
    .cpu_data_o(cpu_data_o1),
    .range(range0),
    .range_out(range1),
    .match_in(match0),
    .match_out(match1),
    .match_is(match_is_1)
    );
rbve_line #(.RANGE_L(224),
            .SUBR(16))
U_line2(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .en_in(match_is_1),
    .lookup_en(lookup_done1),
    .lookup_done(lookup_done2),
    .mod_en(mod_en[2]),
    .odd(odd),
    .addr_loc(addr_loc),
    .cpu_data(cpu_data_d1),
    .cpu_data_o(cpu_data_o2),
    .range(range1),
    .range_out(range2),
    .match_in(match1),
    .match_out(match2),
    .match_is(match_is_2)
    );
rbve_line #(.RANGE_L(208),
            .SUBR(16)) 
U_line3(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .en_in(match_is_2),
    .lookup_en(lookup_done2),
    .lookup_done(lookup_done3),
    .mod_en(mod_en[3]),
    .odd(odd),
    .addr_loc(addr_loc),
    .cpu_data(cpu_data_d1),
    .cpu_data_o(cpu_data_o3),
    .range(range2),
    .range_out(range3),
    .match_in(match2),
    .match_out(match3),
    .match_is(match_is_3)
    );
rbve_line #(.RANGE_L(192),
            .SUBR(16)) 
U_line4(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .en_in(match_is_3),
    .lookup_en(lookup_done3),
    .lookup_done(lookup_done4),
    .mod_en(mod_en[4]),
    .odd(odd),
    .addr_loc(addr_loc),
    .cpu_data(cpu_data_d1),
    .cpu_data_o(cpu_data_o4),
    .range(range3),
    .range_out(range4),
    .match_in(match3),
    .match_out(match4),
    .match_is(match_is_4)
    );
rbve_line #(.RANGE_L(176),
            .SUBR(16)) 
U_line5(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .en_in(match_is_4),
    .lookup_en(lookup_done4),
    .lookup_done(lookup_done5),
    .mod_en(mod_en[5]),
    .odd(odd),
    .addr_loc(addr_loc),
    .cpu_data(cpu_data_d1),
    .cpu_data_o(cpu_data_o5),
    .range(range4),
    .range_out(range5),
    .match_in(match4),
    .match_out(match5),
    .match_is(match_is_5)
    );
rbve_line #(.RANGE_L(160),
            .SUBR(16)) 
U_line6(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .en_in(match_is_5),
    .lookup_en(lookup_done5),
    .lookup_done(lookup_done6),
    .mod_en(mod_en[6]),
    .odd(odd),
    .addr_loc(addr_loc),
    .cpu_data(cpu_data_d1),
    .cpu_data_o(cpu_data_o6),
    .range(range5),
    .range_out(range6),
    .match_in(match5),
    .match_out(match6),
    .match_is(match_is_6)
    );
rbve_line #(.RANGE_L(144),
            .SUBR(16)) 
U_line7(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .en_in(match_is_6),
    .lookup_en(lookup_done6),
    .lookup_done(lookup_done7),
    .mod_en(mod_en[7]),
    .odd(odd),
    .addr_loc(addr_loc),
    .cpu_data(cpu_data_d1),
    .cpu_data_o(cpu_data_o7),
    .range(range6),
    .range_out(range7),
    .match_in(match6),
    .match_out(match7),
    .match_is(match_is_7)
    );
rbve_line #(.RANGE_L(128),
            .SUBR(16)) 
U_line8(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .en_in(match_is_7),
    .lookup_en(lookup_done7),
    .lookup_done(lookup_done8),
    .mod_en(mod_en[8]),
    .odd(odd),
    .addr_loc(addr_loc),
    .cpu_data(cpu_data_d1),
    .cpu_data_o(cpu_data_o8),
    .range(range7),
    .range_out(range8),
    .match_in(match7),
    .match_out(match8),
    .match_is(match_is_8)
    );
// rbve_line_4 U_cos(
rbve_line #(.RANGE_L(112),
            .SUBR(16)) 
U_line9(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .en_in(match_is_8),
    .lookup_en(lookup_done8),
    .lookup_done(lookup_done9),
    .mod_en(mod_en[9]),
    .odd(odd),
    .addr_loc(addr_loc),
    .cpu_data(cpu_data_d1),
    .cpu_data_o(cpu_data_o9),
    .range(range8),
    .range_out(range9),
    .match_in(match8),
    .match_out(match9),
    .match_is(match_is_9)
    );
rbve_line #(.RANGE_L(96),
            .SUBR(16)) 
U_line10(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .en_in(match_is_9),
    .lookup_en(lookup_done9),
    .lookup_done(lookup_done10),
    .mod_en(mod_en[10]),
    .odd(odd),
    .addr_loc(addr_loc),
    .cpu_data(cpu_data_d1),
    .cpu_data_o(cpu_data_o10),
    .range(range9),
    .range_out(range10),
    .match_in(match9),
    .match_out(match10),
    .match_is(match_is_10)
    );
rbve_line #(.RANGE_L(80),
            .SUBR(16)) 
U_line11(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .en_in(match_is_10),
    .lookup_en(lookup_done10),
    .lookup_done(lookup_done11),
    .mod_en(mod_en[11]),
    .odd(odd),
    .addr_loc(addr_loc),
    .cpu_data(cpu_data_d1),
    .cpu_data_o(cpu_data_o11),
    .range(range10),
    .range_out(range11),
    .match_in(match10),
    .match_out(match11),
    .match_is(match_is_11)
    );
rbve_line #(.RANGE_L(64),
            .SUBR(16)) 
U_line12(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .en_in(match_is_11),
    .lookup_en(lookup_done11),
    .lookup_done(lookup_done12),
    .mod_en(mod_en[12]),
    .odd(odd),
    .addr_loc(addr_loc),
    .cpu_data(cpu_data_d1),
    .cpu_data_o(cpu_data_o12),
    .range(range11),
    .range_out(range12),
    .match_in(match11),
    .match_out(match12),
    .match_is(match_is_12)
    );
rbve_line #(.RANGE_L(48),
            .SUBR(16)) 
U_line13(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .en_in(match_is_12),
    .lookup_en(lookup_done12),
    .lookup_done(lookup_done13),
    .mod_en(mod_en[13]),
    .odd(odd),
    .addr_loc(addr_loc),
    .cpu_data(cpu_data_d1),
    .cpu_data_o(cpu_data_o13),
    .range(range12),
    .range_out(range13),
    .match_in(match12),
    .match_out(match13),
    .match_is(match_is_13)
    );
rbve_line #(.RANGE_L(32),
            .SUBR(16)) 
U_line14(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .en_in(match_is_13),
    .lookup_en(lookup_done13),
    .lookup_done(lookup_done14),
    .mod_en(mod_en[14]),
    .odd(odd),
    .addr_loc(addr_loc),
    .cpu_data(cpu_data_d1),
    .cpu_data_o(cpu_data_o14),
    .range(range13),
    .range_out(range14),
    .match_in(match13),
    .match_out(match14),
    .match_is(match_is_14)
    );
// rbve_line_16 U_15(
//     .clk(clk),
//     .rst_n(rst_n),
//     .en_in(match_is_14),
//     .lookup_en(lookup_done14),
//     .lookup_done(lookup_done),
//     .mod_en(mod_en[15]),
//     .addr_loc(addr_loc),
//     .cpu_data(cpu_data_d1),
//     .cpu_data_o(cpu_data_o15),
//     .range(range14),
//     .match_in(match14),
//     .match_out(match15),
//     .match_is(match_is)
//     );
rbve_line_last #(.RANGE_L(16),
                 .SUBR(16)) 
 U_line15(
    .clk(clk),
    .rst_n(rst_n),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .en_in(match_is_14),
    .lookup_en(lookup_done14),
    .lookup_done(lookup_done),
    .mod_en(mod_en[15]),
    .odd(odd),
    .addr_loc(addr_loc),
    .cpu_data(cpu_data_d1),
    .cpu_data_o(cpu_data_o15),
    .range(range14),
    // .range_out(),
    .match_in(match14),
    .match_out(match15),
    .match_is()
    );
//*********************
//MAIN CORE
//********************* 
//\u7ed9 range \u6253\u62cd\uff0c\u548c\u4e0a\u4e00\u7ea7\u7684lookup_done\u4fe1\u53f7\u540c\u65f6\u5230\u8fbe
// assign range0 = (lookup_en)?range:17'b0;
//rbve\u7684\u63a7\u5236\u4fe1\u53f7\u4e3a5\uff0c6\u4f4d
// assign cpu_en_del  = (ram_addr[14]==1)?ram_ctrl[1]:1'b0;
// assign cpu_en_mod  = (ram_addr[14]==1)?ram_ctrl[0]:1'b0;
// assign cpu_en_read = (ram_addr[14]==1)?ram_ctrl[2]:1'b0;
assign cpu_en_mod  = cpu_wen;
assign cpu_en_read1 = cpu_ren1;
assign cpu_en_read2 = cpu_ren2;


// assign addr_loc   = ram_addr[8:0];
// assign rule_loc   = ram_addr[19:15];
// assign ram_loc    = ram_addr[13: 9];
assign ram_loc    = ram_addr[14: 10]; // odd: 14, loc: 13-10, 2022.5.9 xym
always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)
      mod_en <= 0;
    else if(cpu_en_mod)
     case(ram_loc)// odd: 14, loc: 13-10, 2022.5.9 xym
        0,16: mod_en<=16'b0000_0000_0000_0001;
        1,17: mod_en<=16'b0000_0000_0000_0010;
        2,18: mod_en<=16'b0000_0000_0000_0100;
        3,19: mod_en<=16'b0000_0000_0000_1000;
        4,20: mod_en<=16'b0000_0000_0001_0000;
        5,21: mod_en<=16'b0000_0000_0010_0000;
        6,22: mod_en<=16'b0000_0000_0100_0000;
        7,23: mod_en<=16'b0000_0000_1000_0000;
        8,24: mod_en<=16'b0000_0001_0000_0000;
        9,25: mod_en<=16'b0000_0010_0000_0000;
       10,26: mod_en<=16'b0000_0100_0000_0000;
       11,27: mod_en<=16'b0000_1000_0000_0000;
       12,28: mod_en<=16'b0001_0000_0000_0000;
       13,29: mod_en<=16'b0010_0000_0000_0000;
       14,30: mod_en<=16'b0100_0000_0000_0000;
       15,31: mod_en<=16'b1000_0000_0000_0000;
       // 0,1:   mod_en<=16'b0000_0000_0000_0001;
       // 2,3:   mod_en<=16'b0000_0000_0000_0010;
       // 4,5:   mod_en<=16'b0000_0000_0000_0100;
       // 6,7:   mod_en<=16'b0000_0000_0000_1000;
       // 8,9:   mod_en<=16'b0000_0000_0001_0000;
       // 10,11: mod_en<=16'b0000_0000_0010_0000;
       // 12,13: mod_en<=16'b0000_0000_0100_0000;
       // 14,15: mod_en<=16'b0000_0000_1000_0000;
       // 16,17: mod_en<=16'b0000_0001_0000_0000;
       // 18,19: mod_en<=16'b0000_0010_0000_0000;
       // 20,21: mod_en<=16'b0000_0100_0000_0000;
       // 22,23: mod_en<=16'b0000_1000_0000_0000;
       // 24,25: mod_en<=16'b0001_0000_0000_0000;
       // 26,27: mod_en<=16'b0010_0000_0000_0000;
       // 28,29: mod_en<=16'b0100_0000_0000_0000;
       // 30,31: mod_en<=16'b1000_0000_0000_0000;
       default: 
             mod_en <= 0;
     endcase
    else 
      mod_en <=0;
  end
//\u5730\u5740\u4e0e\u8bfb\u51fa\u6570\u636e\u540c\u6b65  \u7528ram_addr_d4[15:14]\u5224\u5b9a\u9ad8\u4e2d\u4f4e32 \u6216 \u9ad8\u4f4e32
always@(posedge clk or negedge rst_n)begin
    if(~rst_n)
      begin
        ram_addr_d1 <= 'd0;
        ram_addr_d2 <= 'd0;
        ram_addr_d3 <= 'd0;
        ram_addr_d4 <= 'd0;
      end
    else 
      begin
        ram_addr_d1 <= ram_addr;
        ram_addr_d2 <= ram_addr_d1;
        ram_addr_d3 <= ram_addr_d2;
        ram_addr_d4 <= ram_addr_d3;
      end
end
//
always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)
      begin
        cpu_en_read1_d1 <= 'd0;
        cpu_en_read1_d2 <= 'd0;
        cpu_en_read1_d3 <= 'd0;
        cpu_en_read1_d4 <= 'd0;
      end
    else 
      begin
        cpu_en_read1_d1 <= cpu_en_read1;
        cpu_en_read1_d2 <= cpu_en_read1_d1;
        cpu_en_read1_d3 <= cpu_en_read1_d2;
        cpu_en_read1_d4 <= cpu_en_read1_d3;
      end
  end

always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)
      read_data_cpuo1 <= 0;
    else if(cpu_en_read1_d3)
     case(ram_addr_d3[14:10])// 2022.5.9 xym
     // case(ram_addr_d3[13:9])//ram_loc
       0:   read_data_cpuo1<=cpu_data_o0;
       1:   read_data_cpuo1<=cpu_data_o1;
       2:   read_data_cpuo1<=cpu_data_o2;
       3:   read_data_cpuo1<=cpu_data_o3;
       4:   read_data_cpuo1<=cpu_data_o4;
       5:   read_data_cpuo1<=cpu_data_o5;
       6:   read_data_cpuo1<=cpu_data_o6;
       7:   read_data_cpuo1<=cpu_data_o7;
       8:   read_data_cpuo1<=cpu_data_o8;
       9:   read_data_cpuo1<=cpu_data_o9;
      10:   read_data_cpuo1<=cpu_data_o10;
      11:   read_data_cpuo1<=cpu_data_o11;
      12:   read_data_cpuo1<=cpu_data_o12;
      13:   read_data_cpuo1<=cpu_data_o13;
      14:   read_data_cpuo1<=cpu_data_o14;
      15:   read_data_cpuo1<=cpu_data_o15;
      //  0:   read_data_cpuo1<=cpu_data_o0;
      //  2:   read_data_cpuo1<=cpu_data_o1;
      //  4:   read_data_cpuo1<=cpu_data_o2;
      //  6:   read_data_cpuo1<=cpu_data_o3;
      //  8:   read_data_cpuo1<=cpu_data_o4;
      // 10:   read_data_cpuo1<=cpu_data_o5;
      // 12:   read_data_cpuo1<=cpu_data_o6;
      // 14:   read_data_cpuo1<=cpu_data_o7;
      // 16:   read_data_cpuo1<=cpu_data_o8;
      // 18:   read_data_cpuo1<=cpu_data_o9;
      // 20:   read_data_cpuo1<=cpu_data_o10;
      // 22:   read_data_cpuo1<=cpu_data_o11;
      // 24:   read_data_cpuo1<=cpu_data_o12;
      // 26:   read_data_cpuo1<=cpu_data_o13;
      // 28:   read_data_cpuo1<=cpu_data_o14;
      // 30:   read_data_cpuo1<=cpu_data_o15;
       default: 
             read_data_cpuo1 <= 0;
     endcase
    else 
      read_data_cpuo1 <=read_data_cpuo1;
  end

always@(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
       read_data_cpu1          <= 'b0;
       read_data_valid1        <= 'b0;
    end
    else if(cpu_en_read1_d4)begin
        case(ram_addr_d4[9:8])// 2022.5.9 xym
        // case(ram_addr_d4[15:14])
          2'b01:begin
            read_data_cpu1   <= read_data_cpuo1[95:64];
            read_data_valid1 <= 1'b1;
          end
          2'b10:begin
            read_data_cpu1   <= read_data_cpuo1[63:32];
            read_data_valid1 <= 1'b1;
          end
          2'b11:begin
            read_data_cpu1   <= read_data_cpuo1[31:0];
            read_data_valid1 <= 1'b1;
          end
          default: begin
            read_data_cpu1   <= read_data_cpu1;
            read_data_valid1 <= 1'b0;
          end
        endcase // ram_addr_d4[15:14]    
    end
    else begin
            read_data_cpu1   <= read_data_cpu1;
            read_data_valid1 <= 1'b0;
    end
end
//
always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)
      begin
        cpu_en_read2_d1 <= 1'b0;
        cpu_en_read2_d2 <= 1'b0;
        cpu_en_read2_d3 <= 1'b0;
        cpu_en_read2_d4 <= 1'b0;
      end
    else 
      begin
        cpu_en_read2_d1 <= cpu_en_read2;
        cpu_en_read2_d2 <= cpu_en_read2_d1;
        cpu_en_read2_d3 <= cpu_en_read2_d2;
        cpu_en_read2_d4 <= cpu_en_read2_d3;
      end
  end
always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)
      read_data_cpuo2 <= 0;
    else if(cpu_en_read2_d3)
     case(ram_addr_d3[14:10])// 2022.5.9 xym
     // case(ram_addr_d3[13:9])//ram_loc
      16:   read_data_cpuo2<=cpu_data_o0;
      17:   read_data_cpuo2<=cpu_data_o1;
      18:   read_data_cpuo2<=cpu_data_o2;
      19:   read_data_cpuo2<=cpu_data_o3;
      20:   read_data_cpuo2<=cpu_data_o4;
      21:   read_data_cpuo2<=cpu_data_o5;
      22:   read_data_cpuo2<=cpu_data_o6;
      23:   read_data_cpuo2<=cpu_data_o7;
      24:   read_data_cpuo2<=cpu_data_o8;
      25:   read_data_cpuo2<=cpu_data_o9;
      26:   read_data_cpuo2<=cpu_data_o10;
      27:   read_data_cpuo2<=cpu_data_o11;
      28:   read_data_cpuo2<=cpu_data_o12;
      29:   read_data_cpuo2<=cpu_data_o13;
      30:   read_data_cpuo2<=cpu_data_o14;
      31:   read_data_cpuo2<=cpu_data_o15;
      //  1:   read_data_cpuo2<=cpu_data_o0;
      //  3:   read_data_cpuo2<=cpu_data_o1;
      //  5:   read_data_cpuo2<=cpu_data_o2;
      //  7:   read_data_cpuo2<=cpu_data_o3;
      //  9:   read_data_cpuo2<=cpu_data_o4;
      // 11:   read_data_cpuo2<=cpu_data_o5;
      // 13:   read_data_cpuo2<=cpu_data_o6;
      // 15:   read_data_cpuo2<=cpu_data_o7;
      // 17:   read_data_cpuo2<=cpu_data_o8;
      // 19:   read_data_cpuo2<=cpu_data_o9;
      // 21:   read_data_cpuo2<=cpu_data_o10;
      // 23:   read_data_cpuo2<=cpu_data_o11;
      // 25:   read_data_cpuo2<=cpu_data_o12;
      // 27:   read_data_cpuo2<=cpu_data_o13;
      // 29:   read_data_cpuo2<=cpu_data_o14;
      // 31:   read_data_cpuo2<=cpu_data_o15;
       default: 
             read_data_cpuo2 <= 0;
     endcase
    else 
      read_data_cpuo2 <=read_data_cpuo2;
  end

always@(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0) begin
       read_data_cpu2          <= 'b0;
       read_data_valid2        <= 'b0;
    end
    else if(cpu_en_read2_d4)begin
        case(ram_addr_d4[9:8])// 2022.5.9 xym
        // case(ram_addr_d4[15:14])
          2'b01:begin
            read_data_cpu2   <= read_data_cpuo2[63:32];
            read_data_valid2 <= 1'b1;
          end
          2'b10:begin
            read_data_cpu2   <= read_data_cpuo2[31:0];
            read_data_valid2 <= 1'b1;
          end
          default: begin
            read_data_cpu2   <= read_data_cpu2;
            read_data_valid2 <= 1'b0;
          end
        endcase // ram_addr_d4[15:14]   
    end
    else begin
        read_data_cpu2   <= read_data_cpu2;
        read_data_valid2 <= 1'b0;
    end
end

always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)
      odd <= 0;
    else 
      odd <= ram_loc[4];// 2022.5.9 xym
      // odd <= ram_loc[0];
  end
always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)
      addr_loc <= 0;
    else 
      addr_loc <= ram_addr[7:0];// 2022.5.9 xym
      // addr_loc <= ram_addr[8:0];
  end
always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)
    begin 
      cpu_data_d1 <= 0;
    end 
    else
    begin  
      cpu_data_d1 <= ram_data    ;
    end 
  end

// always@(posedge clk or negedge rst_n)
//   begin
//      if(~rst_n)
//        valid <=32'hffffffff;
//      else if(cpu_en_del)
//        valid[rule_loc] <= 1'b0;
//      else 
//        valid <= valid;
// end
always@(posedge clk or negedge rst_n)
  begin
     if(~rst_n)
       valid <=32'hffffffff;
     else 
       valid <= valid;
  end
assign match = match15 & valid;
//*********************
endmodule    // hookup byte controller block
    
